MSPI_DebugSop

Revision History

Revision NO.	Description	Data
1.0	Initial release	03/30/2024

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1. Overview

During the use of MSPI, issues do not occur frequently, mostly related to specific scenario requirements. This document provides several situations for reference debugging.

It includes data transmission anomalies, data reception anomalies, communication timeouts, etc., and provides troubleshooting flowcharts and explanations for each step.

The internal registers of mspi on various platforms are generally unchanged, but there may be differences in the CLKGEN, PADMUX, and BDMA registers. Please refer to the actual platform during troubleshooting.

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2. Keyword

• GPIO mode: PAD can be multiplexed into mspi pins through padmux, or it can be set as GPIO pins. When set to GPIO mode, the priority of multiplexing mspi is lower and may be affected.

• PADMUX: The PADMUX setting bank is PADTOP, used to specify the multiplexing relationship.

• CLKGEN: Source clock setting register, used to select the clock source for the IP.

• BDMA: The mspi dma mode requires the BDMA IP to assist in operation, which is responsible for data transfer between memory and mspi.

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3. Data Anomalies

Data transmission anomalies include no waveform, data errors, and individual pins (CS/CK/MOSI) without waveforms. Among them, the absence of a waveform may be accompanied by a timeout error log, which can be checked in the timeout section.

3.1. Troubleshooting Flowchart

Data Anomaly Check Process

3.2. Step Descriptions

Process Node	Node Description	Exit	Required Analysis Data
A	Capture waveform, this is the most intuitive analysis method for communication issues	B C	-
B	Compare waveform analysis with expected data	D E F	-
C	In the case of no waveform, it generally occurs due to pin errors (set as GPIO and pull high/low to confirm if the pin is correct), padmux errors, and clk not being enabled, which prevents communication. It may also be that the set trigger condition happens to be an issue with individual pins. Try setting other pins as trigger conditions. When individual pin anomalies occur, check if GPIO mode is enabled and if there are hardware influences	G H I J	-
D	Data loss, which may be due to incorrect set transmission byte length	K L	mspi bank register bdma bank register
E	Data error	L M	-
F	Whether individual pins have no waveform	N	-
G	Captured waveform pin error, re-confirm with HW which pins should be captured	O	-
H	Incorrect padmux register setting, reconfigure	P	-
I	clkgen not enabled, check CLKGEN register table, confirm if gate bit is open (SPI0 REG:0x1038 0x33 bit[0]; SPI1 REG:0x1038 0x33 bit[8], if the corresponding bit is 1, it indicates clk is disabled)	Q	-
J	The trigger condition pin of LA or oscilloscope happens to be inactive	-	-

4. Timeout

When an mspi timeout error log occurs, it is generally due to unreasonable code trigger timing, both systems having MSPI enabled, or clkgen not being enabled. Please directly provide the code branch, mspi bank, and clkgen bank.

If the riscv side does not have clk when using spi, check if the arm side's spi nodes are all disabled, but the corresponding spi clk nodes in dts need to add the ignore attribute, for example:

pcupid.dtsi

spi0: spi@1f222000 {
        compatible = "sstar,mspi";
        mspi-group = <0>;
        clocks = <&CLK_mspi0>;
        reg = <0x0 0x1F222000 0x0 0x200>;
        #address-cells = <1>;
        #size-cells = <0>;
        interrupts = <GIC_SPI INT_IRQ_MSPI_0 IRQ_TYPE_LEVEL_HIGH>;
        dma-enable;
        cs-num = <1>;
        //cs-ext = <PAD_UNKNOWN>;
        //4to3-mode;
        //clk-out-mode = <27000000>;
        status = "disabled";

        spidev0@0 {
            compatible = "lwn,bk4";
            spi-max-frequency = <2000000>;
            reg = <0>;
        };

    };

pcupid-clks.dtsi

CLK_mspi0: CLK_mspi0 {
    #clock-cells = <0>;
    compatible = "sstar,composite-clock";
    clocks = <&CLK_mpll_432m_div4>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_spi_synth_pll>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
    reg = <0x0 REG_CKG_MSPI0_BASE 0x0 0x4>;
    mux-shift = <2>;  //2+REG_CKG_MSPI0_OFFSET
    mux-width = <3>;
    gate-shift = <0>;  //0+REG_CKG_MSPI0_OFFSET
    // auto-enable = <0>;
    ignore = <1>;
};

5. Register Banks

1. mspi bank

   	mspi0	mspi1
   bank	0x1110	0x1119

2. clkgen bank

   	mspi0	mspi1
   bank	0x1038	0x1038

3. bdma bank

   	bdma	bdma2	bdma3
   bank	0x1002	0x100a	0x100b