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SENSOR USER GUIDE

REVISION HISTORY

Revision No.
Description
 Date
1.0
  • Initial release
    		•  11/19/2025

    1. OVERVIEW

    The sensor padmux is used to configure the multiplexing modes of sensor-related pins to support different hardware circuits and MIPI lane counts.

    Selecting and configuring the correct sensor pin multiplexing mode based on the hardware schematic and pinmux table is the first and most critical step to successfully powering up the sensor.

    2. KEYWORD

    • sensor pad : Sensor hardware Jack location

    3. FUNCTIONAL DESCRIPTION

    The sensor padmux configuration provides the necessary reset and power down pin voltages for sensor power-up and power-down sequences, ensuring compliance with the sensor's required timing. Additionally, it enables I2C pin configuration between the master and slave devices for reading/writing sensor registers.The sensor padmux supports multiple modes, including MIPI mode, and others. By modifying the active mode, the corresponding pins can be used to transmit data into the IC.

    • Different chips support varying MCLK frequencies. The MCLK frequencies supported by iford are as follows:

      supported mclk frequency

    4. HARDWARE CONNECTION OVERVIEW

    4.1. HARDWARE INTERFACE CONFIRMATION

    As shown in the following figure, the BGA11 EVB board supports MIPI0 (4lane) or MIPI00 + MIPI01 (2+2 lane).

    Figure 4-1: BGA11_EVB Board_Hardware Diagram
    Figure 4-2: BGA11_EVB Board mipi pinmux Diagram

    Through the above interfaces, it can be confirmed.

    Panmux mode type 4Lane 2+2Lane
    Pad num snr0 snr0 & snr2
    mipi_rx_mode mode1 mode1 & mode1
    mclk_mode mode1 mode1 & mode1
    rst_mode mode1 mode1 & mode1
    pdn_mode mode0 mode0 & mode0
    I2C_mode I2C1 mode1 I2C1 mode1 & I2C2 mode1

    PS: 1.BGA11 only has MIPI0 4lane snr0 or split into MIPI00 2lane (snr0) + MIPI01 2lane (snr2), so the current 2+2 driver configuration should pay attention to snr0 and snr2.

    snr0 corresponds to snr00, srn2 corresponds to snr01. iford supports MIPI0 (4lane) at the highest specification. MIPI0 can be split into MIPI00 and MIPI01 -- snr00 and snr01.

    4.2. MIPI INTERFACE LINE SEQUENCE MATCHING

    The five positions in csi_sr0_lane_select correspond to \< CLK, DataLane0, DataLane1, DataLane2, DataLane3> of MIPI CSI rx aphy respectively.

    As BGA11 the figure, the sensor-side pin arrangement. Clk is mapping to CH2, DataLane0 is mapping to CH1, DataLane1 is mapping to CH3, DataLane2 is mapping to CH0, DataLane3 is mapping to CH4, so csi_sr0_lane_select = <2 1 3 0 4>.

    Figure 4-3: MIPI0 4lane mapping

    The five positions in csi_sr0_lane_select correspond to \< CLK, DataLane0, DataLane1, DataLane2, DataLane3> of MIPI CSI rx aphy respectively.

    The three positions in csi_sr2_lane_select correspond to \< CLK, DataLane0, DataLane1> of MIPI CSI rx aphy respectively.

    As shown in the following BGA11 MIPI00 2lane(snr0) + MIPI01 2lane(snr2) figure on the BGA11 mainboard.

    MIPI00 2lane(snr0) Clk is mapping to CH2, DataLane0 is mapping to CH0, DataLane1 is mapping to CH1, so csi_sr0_lane_select = <2 1 0 3 4>, If the MIPI data/clk lane pn are reversed, then you need to configure , csi_sr0_lane_pn_swap = <1 1 1 1 1>;

    MIPI01 2lane(snr2) Clk is mapping to CH2, DataLane0 is mapping to CH0, DataLane1 is mapping to CH1, so csi_sr2_lane_select = <2 1 0>, If the MIPI data/clk lane pn are reversed, then you need to configure , csi_sr2_lane_pn_swap = <1 1 1>;

    Figure 4-4:MIPI0 2lane mapping
        lane order modification
    ./riu_r 0x1538 0x6 0xA 0xE 0x22 0x25, bit[12:15] to check if the order is effective
    0x1538 is sensor0
    0x153c is sensor2

    PS: Since modifying the sensor line sequence requires replacing the kernel, it is more troublesome. You can quickly confirm the line sequence in the following way.

    Configure by loading insmod /config/modules/5.10/mi_sensor.ko gp_sntExternalConfig=/customer/sensorpad0_2lane.json to load json.

    For example:

    imx307 2lane line sequence 1 0 2:

        {
        "SensorIF": [
            {
                "sensorPad": 0,
                "hwClass": "mipi",
                "content": {
                    "lane_number": 2,
                    "hdr_lane_number": 2,
                    "lane_select": "1,0,2",
                    "lane_swap": "0,0,0"
                }
            }
        ]
    }

    5. KERNEL USAGE GUIDE

    5.1. DTS CONFIGURATION

    4lane:

        csi: csi {
                compatible = "sgs,csi";
                io_phy_addr = <0x1f000000>;
                banks = <0x153C>,<0x153D>,<0x153E>,<0x1538>,<0x153A>,<0x153B>;
                atop_banks = <0x153F>;
                clkgen_banks = <0x1038>;
                interrupts=  <GIC_SPI INT_IRQ_MIPI_CSI2 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&CLK_csi0_mac_lptx_top_i>,<&CLK_csi0_mac_top_i>,<&CLK_csi0_ns_top_i>,<&CLK_csi1_mac_lptx_top_i>,<&CLK_csi1_mac_top_i>,<&CLK_csi1_ns_top_i>;
                status = "ok";
                /* Config max lane number */
                csi_sr0_lane_num = <4>;
                /* Config lane selection */
                csi_sr0_lane_select = <2 1 3 0 4>;
                /* Config lane P/N swap */
                csi_sr0_lane_pn_swap = <1 1 1 1 1>;
            };
    sensorif: sensorif {
                compatible = "sgs,sensorif";
                status = "ok";
                clocks = <&CLK_sr00_mclk>, <&CLK_sr01_mclk>;

                /* Config sensor 0 pad mux */
                snr_sr0_mipi_mode         = <1>;
                snr_sr0_mipi_rst_mode     = <1>;
                snr_sr0_mipi_pdn_mode     = <0>;
                snr_sr0_mipi_mclk_mode    = <1>;
                snr_sr0_rst_gpio          = <-1>;
                snr_sr0_pdn_gpio          = <-1>;

                /* Config mclk 37.125MHz supported */
                snr_sr0_mclk_37p125 = <1>;

                /* Config i2c for sensor pad */
                snr0_mipi_i2c = <0>;
            };

    2+2lane:

        csi: csi {
                compatible = "sgs,csi";
                io_phy_addr = <0x1f000000>;
                banks = <0x153C>,<0x153D>,<0x153E>,<0x1538>,<0x153A>,<0x153B>;
                atop_banks = <0x153F>;
                clkgen_banks = <0x1038>;
                interrupts=  <GIC_SPI INT_IRQ_MIPI_CSI2 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&CLK_csi0_mac_lptx_top_i>,<&CLK_csi0_mac_top_i>,<&CLK_csi0_ns_top_i>,<&CLK_csi1_mac_lptx_top_i>,<&CLK_csi1_mac_top_i>,<&CLK_csi1_ns_top_i>;
                status = "ok";
                /* Config max lane number */
                csi_sr0_lane_num = <2>;
                csi_sr2_lane_num = <2>;
                /* Config lane selection */
                csi_sr0_lane_select = <2 1 0 3 4>;
                csi_sr2_lane_select = <2 1 0>;
                /* Config lane P/N swap */
                csi_sr0_lane_pn_swap = <0 0 0 0 0>;
                csi_sr2_lane_pn_swap = <0 0 0>;
            };
    sensorif: sensorif {
                compatible = "sgs,sensorif";
                status = "ok";
                clocks = <&CLK_sr00_mclk>, <&CLK_sr01_mclk>;

                /* Config sensor 0 pad mux */
                snr_sr0_mipi_mode         = <1>;
                snr_sr0_mipi_rst_mode     = <1>;
                snr_sr0_mipi_pdn_mode     = <0>;
                snr_sr0_mipi_mclk_mode    = <1>;
                snr_sr0_rst_gpio          = <-1>;
                snr_sr0_pdn_gpio          = <-1>;

                /* Config sensor 2 pad mux */
                snr_sr2_mipi_mode         = <1>;
                snr_sr2_mipi_rst_mode     = <1>;
                snr_sr2_mipi_pdn_mode     = <0>;
                snr_sr2_mipi_mclk_mode    = <1>;
                snr_sr2_rst_gpio          = <-1>;
                snr_sr2_pdn_gpio          = <-1>;

                /* Config mclk 37.125MHz supported */
                snr_sr0_mclk_37p125 = <1>;
                snr_sr2_mclk_37p125 = <1>;

                /* Config i2c for sensor pad */
                snr0_mipi_i2c = <1>;
                snr2_mipi_i2c = <2>;
            };

    The definitions of the CSI section are as follows:

    Parameter Definition Remark
    interrupts mipi rx csi interrupt No need for modification.
    clocks mipi rx csi clock source No need for modification.
    csi_sr0_lane_num number of mipi sensor pad0 signal lines The settings need to be configured based on the actual number of signal lines used by the MIPI sensor, refer to 2.3.
    csi_sr0_lane_select Configure the MIPI signal line order for sensor pad0 Modifications need to be made based on the actual MIPI signal line order of the board and the sensor module, refer to 2.3.
    csi_sr0_lane_pn_swap Configure the power polarity of the MIPI signal lines for sensor pad0 When configured to 1, it indicates that the power polarity of a set of MIPI signals is swapped, refer to 2.3.
    csi_sr2_lane_select Configure the MIPI signal line order for sensor pad2 Modifications need to be made based on the actual MIPI signal line order of the board and the sensor module, refer to 2.3.
    csi_sr2_lane_num number of mipi sensor pad2 signal lines The settings need to be configured based on the actual number of signal lines used by the MIPI sensor, refer to 2.3.
    csi_sr2_lane_pn_swap Configure the power polarity of the MIPI signal lines for sensor pad2 When configured to 1, it indicates that the power polarity of a set of MIPI signals is swapped, refer to 2.3.

    The definitions of the sensorif section are as follows:

    Parameter Definition Remark
    clocks sensor mclk clock source The configuration needs to be done in the order of pad0 and pad2.
    snr_sr0_mipi_mode mipi sensor pad0 mipi mode Refer to Section 1.
    snr_sr0_mipi_rst_mode mipi sensor pad0 reset mode Refer to Section 1.
    snr_sr0_mipi_pdn_mode mipi sensor pad0 pdn mode Refer to Section 1.
    snr_sr0_mipi_mclk_mode mipi sensor pad0 mclk mode Refer to Section 1.
    snr_sr0_rst_gpio mipi sensor pad0 reset gpio pin setting When configuring both rst mode and rst gpio, prioritize the gpio settings.
    snr_sr0_pdn_gpio mipi sensor pad0 pdn gpio pin setting When configuring both rst mode and rst gpio, prioritize the gpio settings.
    snr_sr0_mclk_37p125 configuration to support sensor pad0 to use 37.125MHz mclk
    snr0_mipi_i2c configuration for mipi sensor pad0 i2c bus id The configuration needs to be based on the actual I2C bus being used.

    5.2. IIC CONFIGURATION

    As shown in the previous section: In the case of 4lane, snr0 is bound to i2c1 mode1. In the case of 2+2lane, snr00 and snr01 are bound to i2c1 mode1 and i2c2 mode1.

        snr0_mipi_i2c = <1>;
    snr2_mipi_i2c = <2>;

    snr0 stands for MIPI sensor 0

    <1> stands for using I2C bus 1

    I2C padmux is configured in the dtsi corresponding to padmux under kernel\arch\arm64\boot\dts\sgs:

        //I2C1 Mode1,sensorif_mipi_grp1_i2c
            <PAD_GPIOB_00            PINMUX_FOR_I2C0_MODE_1           MDRV_PUSE_I2C1_SCL>,
            <PAD_GPIOB_01            PINMUX_FOR_I2C0_MODE_1           MDRV_PUSE_I2C1_SDA>,
    //I2C2 Mode1,sensorif_mipi_grp0_i2c
            <PAD_GPIOB_04            PINMUX_FOR_I2C1_MODE_1           MDRV_PUSE_I2C2_SCL>,
            <PAD_GPIOB_05            PINMUX_FOR_I2C1_MODE_1           MDRV_PUSE_I2C2_SDA>,

    I2c1: /customer/riu_r 0x103c 53 //Whether bit[0:1] is the value of the corresponding mode

    I2c2: trust zone config

    5.3. SENSOR DRIVER LOADING

    5.3.1 SENSOR DRIVER CONFIGURATION

        insmod /config/modules/5.10/imx307_MIPI.ko chmap=1
    chmap mens bit map for configuration
    sensor 0 bit[0]----> chmap=1
    sensor 2 bit[2]----> chmap=4

    To modify the default supported sensor drivers and pre-installed sensor drivers in the kernel, you can use the menuconfig interface.

    1. enter alkaid project root directory, make menuconfig

    2. press Enter to choose Sensor sub-options

    3. press Enter to choose Sensor List sub-options, and write required sensor driver names

    4. After editing, exit and press Enter to enter the Sensor0 submenu. Then, specify the names of the sensor drivers to be pre-loaded with insmod.

    5. After completing the edits, exit and press Enter to enter the 'Sensor0 Opt' submenu. Then configure the parameters required for the pre-loaded sensor0 driver.

    After compilation, the selected sensor drivers from the Sensor List will be generated under /config/modules/5.10/. Additionally, you will find the pre-configured insmod command for sensor0 in /customer/demo.sh.

    5.3.2. SENSOR IQ FILE CONFIGURATION

    The default sensor IQ (Image Quality) files supported by the image can be modified via menuconfig.

    1. enter alkaid project root directory, make menuconfig

    2. press Enter to choose Sensor sub-options

    3. Press Enter to enter the IQ0 submenu, then specify the IQ file name to be used. The numerical suffix after "IQ" corresponds to different sensor pads (e.g., IQ0 maps to sensor0).

    Upon successful compilation, the selected IQ file for IQ0 will be generated under /config/modules/iqfile/.

    5.4. PART OF SENSOR DRIVER FUNCTION INTRODUCTION

    Handle of mipi sensor interface register lists

    Parameter Definition Remark
    handle->interface_attr.attr_mipi.mipi_lane_num Register set MIPI lane number Default : 4
    handle->interface_attr.attr_mipi.mipi_data_format Register set MIPI data format CUS_SEN_INPUT_FORMAT_YUV422,
    CUS_SEN_INPUT_FORMAT_RGB,
    handle->interface_attr.attr_mipi.mipi_yuv_order Register set MIPI yuv order For yuv sensor only
    handle->interface_attr.attr_mipi.mipi_hdr_mode Register set MIPI HDR mode CUS_HDR_MODE_NONE
    /No HDR/
    CUS_HDR_MODE_SONY_DOL
    /Sony standard Line information output/
    CUS_HDR_MODE_DCG
    /Dual Gain HDR/
    CUS_HDR_MODE_EMBEEDED_RAW8
    /Embedded 8bit HDR/
    CUS_HDR_MODE_EMBEEDED_RAW10
    /Embedded 10bit HDR/
    CUS_HDR_MODE_EMBEEDED_RAW12
    /Embedded 12bit HDR/
    CUS_HDR_MODE_EMBEEDED_RAW14
    /Embedded 14bit HDR/
    CUS_HDR_MODE_EMBEEDED_RAW16
    /Embedded 16bit HDR/
    CUS_HDR_MODE_COMP
    /Compress HDR/
    CUS_HDR_MODE_LI
    /Line Interleaved HDR/
    CUS_HDR_MODE_COMP_VS
    /Compress HDR + very short/
    CUS_HDR_MODE_VC
    /Virtual Channel mode/
    CUS_HDR_MODE_MAX
    NOTE:
    In the old platform, CUS_HDR_MODE_DCG represented virtual channel HDR, and in the new platform it needs to rename CUS_HDR_MODE_VC.
    handle->interface_attr.attr_mipi.mipi_hdr_virtual_channel_num Register set HDR virtual channel number Based on each sensor VC mode header define For example imx415:
    Long Exposure Frame : 0
    Short Exposure Frame : 1
    handle->interface_attr.attr_mipi.mipi_hdr_fusion_type Register set HDR fusion type CUS_HDR_FUSION_TYPE_NONE,(default)
    CUS_HDR_FUSION_TYPE_2T1,
    CUS_HDR_FUSION_TYPE_3T1,

    mipi csi callback function lists

    Parameter Definition Remark
    sensor_if->SetCSI_Clk (u32 idx, CUS_CSI_CLK clk) Parameter:
    idx : Sensor Pad
    CUS_CSI_CLK : Mipi clk
    Set MIPI Interface MAC CLK    		 Callback to CSI driver
    sensor_if->SetCSI_Lane(u32 idx, u16 num_lane, u8 bon_off) Parameter:
    idx : Sensor Pad
    num_lane : Mipi lane number
    bon_off : Enable or disable
    Set MIPI Interface Data Lane    		 Callback to CSI driver
    sensor_if->SetCSI_hdr_mode(idx, CUS_HDR_MODE hdr_mode, u8 bon_off) Parameter:
    idx : Sensor Pad
    hdr_mode :
    bon_off : Enable or disable
    Set HDR Data Format    		 Callback to CSI driver
    CUS_HDR_MODE_NONE
    /No HDR/
    CUS_HDR_MODE_SONY_DOL
    /Sony standard Line information output/
    CUS_HDR_MODE_DCG
    /Dual Gain HDR/
    /Embedded 16bit HDR/
    CUS_HDR_MODE_COMP
    /Compress HDR/
    CUS_HDR_MODE_LI
    /Line Interleaved HDR/
    CUS_HDR_MODE_COMP_VS
    /Compress HDR + very short/
    CUS_HDR_MODE_VC
    /Virtual Channel mode/
    CUS_HDR_MODE_MAX
    sensor_if->SetCSI_LongPacketType(u32 idx, u16 dt0_15, u16 dt16_31, u16 u32_47) Parameter:
    idx : Sensor Pad
    Type [15:0], [31:16], [47:32]
    Set MIPI Long Packet Type enable    		 Callback to CSI driver long packet type enable
    [0]: Null
    [1]: blinking
    [2]: embedded
    [14]: YUV422_8B
    [26]: RAW8
    [27]: RAW10
    [28]: RAW12
    [29]: RAW14
    [30]: RAW16
    [32]: UD1
    [33]: UD2
    [34]: UD3
    [35]: UD4
    [36]: UD5
    [37]: UD6
    [38]: UD7
    [39]: UD8
    Sensor_if->SetCSI_yuv_order_swap(u32 idx, u8 swap) Parameter:
    idx : Sensor Pad
    swap: Enable or disable
    Set MIPI Input YUV422 data order swap    		 Callback to CSI driver

    Handle of sensorif callback function lists

    Parameter Definition Remark
    sensor_if->PowerOff(u32 idx, CUS_CLK_POL pol); Parameter:
    idx : Sensor Pad
    CUS_CLK_POL : Pull high or pull low
    Set Sensor-IF PowerDown pull high or not.    		 Callback to VIF driver
    sensor_if->Reset(u32 idx, CUS_CLK_POL pol); Parameter:
    idx : Sensor Pad
    CUS_CLK_POL : Pull high or pull low
    Set Sensor-IF SW RESET pull high or not.    		 Callback to VIF driver
    sensor_if->MCLK(u32 idx , u8 bon_off, CUS_MCLK_FREQ mclk); Parameter:
    idx : Sensor Pad
    bon_off : Enable or disable
    CUS_MCLK_FREQ : Sensor clk
    Register set VIF module output MCLK to sensor For MI Query!!    		 Main Chip Support MCLK List as :
    CUS_CMU_CLK_27MHZ,
    CUS_CMU_CLK_21P6MHZ,
    CUS_CMU_CLK_12MHZ,
    CUS_CMU_CLK_5P4MHZ,
    CUS_CMU_CLK_36MHZ,
    CUS_CMU_CLK_54MHZ,
    CUS_CMU_CLK_43P2MHZ,
    CUS_CMU_CLK_61P7MHZ,
    CUS_CMU_CLK_72MHZ,
    CUS_CMU_CLK_48MHZ,
    CUS_CMU_CLK_24MHZ,
    CUS_CMU_CLK_37P125MHZ,
    CUS_CMU_CLK_LPLL_DIV1,
    CUS_CMU_CLK_LPLL_DIV2,
    CUS_CMU_CLK_LPLL_DIV4,
    CUS_CMU_CLK_LPLL_DIV8,
    sensor_if->SetIOPad (u32 idx, CUS_SENIF_BUS ulSnrType, NULL) Parameter:
    idx : Sensor Pad
    CUS_SENIF_BUS : Sensor interface
    For SENSOR-IF I/O Bus Mode    		 Callback to VIF driver
    sensor_if->SetSkipFrame(u32 idx, u16 skip_num, u8 bon_off) Parameter:
    idx : Sensor Pad
    skip_num : skip frame cnt
    bon_off : Enable or disable
    Skip vif output frame    		 Callback to VIF driver

    more detail, please refer toSensor_Porting_Guide

    5.5. SENSOR DRIVER DEVELOPMENT

    The implementation of different types of sensor drivers is essentially similar. For specific details, please refer toSensor_Guide

    5.6. SAMPLE CODE

    snr vif init function

        MI_S32 ST_VifInit(ST_Stream_Attr_T *pStreamAttr)
    {
        /************************************************
        Step1:  Init Sensor
        *************************************************/
        MI_SNR_PADInfo_t stSnrPadInfo;
        MI_SNR_PlaneInfo_t stSnrPlaneInfo;


        MI_SNR_PADID snrPadId = pStreamAttr->u32SnrId;
        MI_U32 u32ResCount = 0;

        memset(&stSnrPadInfo, 0x0, sizeof(MI_SNR_PADInfo_t));
        memset(&stSnrPlaneInfo, 0x0, sizeof(MI_SNR_PlaneInfo_t));

        ExecFunc(MI_SNR_SetPlaneMode(snrPadId, FALSE), DRM_SUCCESS);
        ExecFunc(MI_SNR_QueryResCount(snrPadId, &u32ResCount), DRM_SUCCESS);

        if(pStreamAttr->u32SnrChoiceRes > u32ResCount-1){
            printf("MI_SNR_QueryResCount :%d\n", u32ResCount);
            return -1;
        }

        ExecFunc(MI_SNR_SetRes(snrPadId, pStreamAttr->u32SnrChoiceRes), DRM_SUCCESS);
        ExecFunc(MI_SNR_Enable(snrPadId), DRM_SUCCESS);

        /************************************************
        Step2:  Init Vif
        *************************************************/
        MI_VIF_GROUP VifGroupId = 0;
        MI_VIF_DEV VifDevId = 0;
        MI_VIF_DEV VifChnId = pStreamAttr->VifChnId;
        MI_VIF_PORT VifPortId = pStreamAttr->VifPortId;
        MI_VIF_GroupAttr_t stVifGroupAttr;
        MI_VIF_DevAttr_t stVifDevAttr;
        MI_VIF_OutputPortAttr_t stVifPortAttr;

        get_vif_from_snrpad(snrPadId, &VifGroupId, &VifDevId);


        memset(&stVifGroupAttr, 0x0, sizeof(MI_VIF_GroupAttr_t));
        memset(&stVifDevAttr, 0x0, sizeof(MI_VIF_DevAttr_t));
        memset(&stVifPortAttr, 0x0, sizeof(MI_VIF_OutputPortAttr_t));

        ExecFunc(MI_SNR_GetPadInfo(snrPadId, &stSnrPadInfo), DRM_SUCCESS);
        ExecFunc(MI_SNR_GetPlaneInfo(snrPadId, 0, &stSnrPlaneInfo), DRM_SUCCESS);
        printf(
                    "MI_SNR_GetPlaneInfo %d, outputsize(%d, %d, %d, %d)\n",
                    snrPadId,stSnrPlaneInfo.stCapRect.u16X,stSnrPlaneInfo.stCapRect.u16Y,
                    stSnrPlaneInfo.stCapRect.u16Width,stSnrPlaneInfo.stCapRect.u16Height);

        stVifGroupAttr.eIntfMode = E_MI_VIF_MODE_MIPI;
        stVifGroupAttr.eWorkMode = E_MI_VIF_WORK_MODE_1MULTIPLEX;
        stVifGroupAttr.eHDRType = E_MI_VIF_HDR_TYPE_OFF;
        if (stVifGroupAttr.eIntfMode == E_MI_VIF_MODE_BT656) {
            stVifGroupAttr.eClkEdge = (MI_VIF_ClkEdge_e)stSnrPadInfo.unIntfAttr.stBt656Attr.eClkEdge;
        } else {
            stVifGroupAttr.eClkEdge = E_MI_VIF_CLK_EDGE_DOUBLE;
        }

        ExecFunc(MI_VIF_CreateDevGroup(VifGroupId, &stVifGroupAttr), DRM_SUCCESS);
        stVifDevAttr.stInputRect.u16X = stSnrPlaneInfo.stCapRect.u16X;
        stVifDevAttr.stInputRect.u16Y = stSnrPlaneInfo.stCapRect.u16Y;
        stVifDevAttr.stInputRect.u16Width = stSnrPlaneInfo.stCapRect.u16Width;
        stVifDevAttr.stInputRect.u16Height = stSnrPlaneInfo.stCapRect.u16Height;
        if (stSnrPlaneInfo.eBayerId >= E_MI_SYS_PIXEL_BAYERID_MAX) {
            stVifDevAttr.eInputPixel = stSnrPlaneInfo.ePixel;
        } else {
            stVifDevAttr.eInputPixel = (MI_SYS_PixelFormat_e)RGB_BAYER_PIXEL(
                    stSnrPlaneInfo.ePixPrecision, stSnrPlaneInfo.eBayerId);
        }
        ExecFunc(MI_VIF_SetDevAttr(VifDevId, &stVifDevAttr), DRM_SUCCESS);
        ExecFunc(MI_VIF_EnableDev(VifDevId), DRM_SUCCESS);
        stVifPortAttr.stCapRect.u16X = stSnrPlaneInfo.stCapRect.u16X;
        stVifPortAttr.stCapRect.u16Y = stSnrPlaneInfo.stCapRect.u16Y;
        stVifPortAttr.stCapRect.u16Width = stSnrPlaneInfo.stCapRect.u16Width;
        stVifPortAttr.stCapRect.u16Height = stSnrPlaneInfo.stCapRect.u16Height;
        stVifPortAttr.stDestSize.u16Width = stSnrPlaneInfo.stCapRect.u16Width;
        stVifPortAttr.stDestSize.u16Height = stSnrPlaneInfo.stCapRect.u16Height;
        stVifPortAttr.eFrameRate = E_MI_VIF_FRAMERATE_FULL;
        if (stSnrPlaneInfo.eBayerId >= E_MI_SYS_PIXEL_BAYERID_MAX) {
            stVifPortAttr.ePixFormat = stSnrPlaneInfo.ePixel;
        } else {
            stVifPortAttr.ePixFormat = (MI_SYS_PixelFormat_e)RGB_BAYER_PIXEL(
                    stSnrPlaneInfo.ePixPrecision, stSnrPlaneInfo.eBayerId);
        }
        ExecFunc(MI_VIF_SetOutputPortAttr(VifDevId, VifPortId, &stVifPortAttr), DRM_SUCCESS);


        return 0;
    }

    6. SENSOR SUPPORT LIST

    6.1. MIPI Interface Camera Sensor Support list

    During the chip verification phase, the verified MIPI interface sensors are shown in the following table:

    Interface Type Lane Count Type Key Indicators Data Format Souffle Iford
    MIPI 4Lane IMX415 3840x2160@30FPS, 3F HDR, 4lane Bayer Pass Pass
    SC450AI 2688x1520@60FPS, 4lane Bayer Pass Pass
    SC830AI 3840x2160@30FPS, 4lane Bayer Pass None
    OS08A10 3840x2160@60FPS, 4lane Bayer Pass None
    OS12D40 4512x2512@30fps, 4lane Bayer Pass None
    OS04C10 2560x1440@30fps, 4lane Bayer Pass None
    IMX675 2592x1944@30fps, HDR, 4lane Bayer Pass None
    IMX485 3840x2160@30FPSs, HDR, 4lane Bayer Pass None
    AR0830 3848x2168@30FPSs, HDR, 4lane Bayer Pass None
    OS05A10 2592x1944@30FPSs, 4lane Bayer Pass None
    2lane/4lane IMX307 1920x1080@30FPS, 2F HDR, 2/4lane Bayer Pass Pass
    OS04A10 2688x1520@30FPS, 2lane/4lane Bayer Pass None
    1 lane OG0VA1B 1920x1080@30FPS, 1lane Bayer Pass None

    7. FAQ

    Q1: How to check sensor output image

    echo dumptaskfile 0 2 /mnt/pcm > /proc/mi_modules/mi_isp/mi_isp0

    echo dumptaskfile 0 2 /mnt/pcm > /proc/mi_modules/mi_scl/mi_scl0

    /mnt/pcm : image dump path
2: catch 2 frame
0: chnNum

    Q2: How to confirm sensor interrupt info

    please refer to MI VIF API 5.PROCFS INTRODUCTION