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SATA Host User Guide

REVISION HISTORY

Revision No.
Description
 Date
1.0
  • Initial release
    		•  01/06/2026
    1.1
  • Updated CTS setting process order: set transfer speed (test_gen) before test pattern (cts_pattern)
    		•  05/11/2026

    1. Overview

    This document introduces the usage of the SATA Host controller on the Mhera platform, including configuration instructions for both U-Boot and Kernel stages.

    The SATA controller consists of the following two main modules:

    • AHCI Controller: Advanced Host Controller Interface, responsible for SATA protocol handling

    • SATA PHY: Physical Layer interface, responsible for signal transmission and electrical characteristics control

    💡 Note: The Mhera platform supports two independent SATA Ports, allowing simultaneous connection of two SATA devices.

    2. Key Terms

    Term Full Name Description
    AHCI Advanced Host Controller Interface Advanced Host Controller Interface, defines the communication specification between host controller and SATA devices
    ATA Advanced Technology Attachment Interface standard for connecting storage devices like HDDs
    SATA Serial ATA Serial ATA, a bus interface that uses serial transmission for data
    PHY Physical Layer Physical layer, responsible for signal encoding, decoding, and transmission
    PMP Port Multiplier Port Multiplier, used to expand the number of SATA interfaces
    FBS FIS-Based Switching FIS-Based Switching mechanism, improves PMP performance

    3. Features

    ✅ Device Support

    • Supports standard SATA devices such as HDD (Hard Disk Drive), SSD (Solid State Drive), CD-ROM, etc.
    • Supports Port Multiplier (PMP) to expand a single SATA interface for connecting multiple devices

    ✅ Transfer Rates

    • Supports SATA GEN1 (1.5 Gbps)
    • Supports SATA GEN2 (3.0 Gbps)
    • Supports SATA GEN3 (6.0 Gbps)

    ✅ Hardware Specifications

    • Mhera platform provides 2 independent SATA Ports
    • Each Port is equipped with independent PHY and AHCI controller
    • Supports DMA coherency (dma-coherent) optimization

    4. U-Boot Usage

    This section introduces the configuration and usage of the SATA Host driver during the U-Boot stage.

    4.1 Driver Configuration

    4.1.1 menuconfig Configuration

    Execute make menuconfig in the U-Boot source directory and enable the SATA driver following the path below:

    Device Drivers
└── [*] Sgs drivers  --->
    ├── [*]   Sgs ACP Bridge driver
    └── [*]   Sgs SATA HOST
        ├── [*]     Sgs sata apply hd link
        └── [*]     Sgs sata apply hd link vote

    ⚠️ Note: All the above options must be selected to fully enable SATA Host functionality.

    4.1.2 DTS Node Configuration

    Add the following node configuration in the U-Boot device tree file. Note: U-Boot and Kernel DTS configurations are slightly different.

    4.1.2.1 SATA Port0 Configuration
    /* SATA Port0 PHY configuration */
sgs_sataphy: sgs-sata-phy {
    compatible = "sgs,sataphy";
    reg-names = "phyd", "phya", "ahci_misc", "phya2";
    reg = <0x1F287600 0x200>, <0x1F287800 0x200>, <0x1F287400 0x200>, <0x1F287a00 0x200>;
    phy_mode = <2>;                      /* PHY rate mode: 0=GEN1, 1=GEN2, 2=GEN3 */
    tx_ssc_mode = <0>;                   /* Spread spectrum clock: 0=disabled, 1=enabled */
    tx_gen1_gen2_Vpp = <0xFF>,<0xFF>;    /* GEN1/GEN2 transmit voltage swing (0xFF=default) */
    tx_gen3_de_emphasis = <0xFF>,<0xFF>,<0xFF>;  /* GEN3 de-emphasis parameters */
    rx_eq_rs1 = <0xFF>,<0xFF>,<0xFF>;    /* Receive equalization parameter RS1 */
    rx_eq_rs2 = <0xFF>,<0xFF>,<0xFF>;    /* Receive equalization parameter RS2 */
    rx_eq_ctle = <0xFF>;                 /* Receive equalization parameter CTLE */

    port_id = <0>;                       /* Port number: 0 indicates first SATA */
    #phy-cells = <0>;
    status = "okay";
};

/* SATA Port0 AHCI controller configuration */
sata {
    compatible = "sgs,sata";
    reg-names = "ahci", "ahci_port0";
    reg = <0x1F346800 0x100>, <0x1F346900 0x100>;
    phy-names = "sataphy";
    phys = <&sgs_sataphy>;               /* Reference to corresponding PHY node */
    fbs_mode;                            /* Enable FIS-Based Switching mode */
    sata_acp;                            /* Enable ACP mode */
    dma-coherent;                        /* Enable DMA coherency optimization */
    status = "okay";
};
    4.1.2.2 SATA Port1 Configuration
    /* SATA Port1 PHY configuration */
sgs_sata1phy: sgs-sata1-phy {
    compatible = "sgs,sataphy";
    reg-names = "phyd", "phya", "ahci_misc", "phya2";
    reg = <0x1F288400 0x200>, <0x1F288600 0x200>, <0x1F288200 0x200>, <0x1F288800 0x200>;
    phy_mode = <2>;
    tx_ssc_mode = <0>;
    tx_gen1_gen2_Vpp = <0xFF>,<0xFF>;
    tx_gen3_de_emphasis = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_rs1 = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_rs2 = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_ctle = <0xFF>;
    port_id = <1>;                       /* Port number: 1 indicates second SATA */
    #phy-cells = <0>;
    status = "okay";
};

/* SATA Port1 AHCI controller configuration */
sata1 {
    compatible = "sgs,sata";
    reg-names = "ahci", "ahci_port0";
    reg = <0x1F346A00 0x100>, <0x1F346B00 0x100>;
    phy-names = "sataphy";
    phys = <&sgs_sata1phy>;              /* Reference to corresponding PHY node */
    fbs_mode;
    sata_acp;
    dma-coherent;
    status = "okay";
};

    4.1.3 DTS Parameter Description

    4.1.3.1 AHCI Controller Parameters
    Property Description Needs Modification
    compatible Used for driver matching, identifies device type ❌ Do not modify
    reg-names Register region name list ❌ No need to modify
    reg Register address and size ❌ No need to modify
    phy-names PHY name list ❌ No need to modify
    phys Referenced PHY node ❌ No need to modify
    fbs_mode Enable FIS-Based Switching mode ❌ No need to modify
    sata_acp Enable ACP mode ❌ No need to modify
    dma-coherent Enable DMA coherency optimization ❌ No need to modify
    status Device status ("okay"/"disabled") ✅ Optional modification
    4.1.3.2 PHY Parameters
    Property Description Configurable Values Needs Modification
    compatible Used for driver matching "sgs,sataphy" ❌ Do not modify
    reg Register address and size Fixed address ❌ No need to modify
    reg-names Register region name list "phyd","phya","ahci_misc","phya2" ❌ No need to modify
    phy_mode PHY rate mode 0=GEN1, 1=GEN2, 2=GEN3 ✅ Modify based on requirements
    tx_ssc_mode Spread spectrum clock mode 0=disabled, 1=enabled ✅ Modify based on requirements
    tx_gen1_gen2_Vpp GEN1/GEN2 transmit voltage swing 0xFF=default ✅ Adjust based on signal quality
    tx_gen3_de_emphasis GEN3 de-emphasis parameters See Section 6 CTS settings ✅ Adjust based on signal quality
    rx_eq_rs1 Receive equalization parameter RS1 See Section 6 CTS settings ✅ Adjust based on signal quality
    rx_eq_rs2 Receive equalization parameter RS2 See Section 6 CTS settings ✅ Adjust based on signal quality
    rx_eq_ctle Receive equalization parameter CTLE See Section 6 CTS settings ✅ Adjust based on signal quality
    port_id Port number 0=Port0, 1=Port1 ❌ No need to modify
    status PHY enable status "okay" / "disabled" ✅ Optional modification

    💡 Note: The 0xFF value in PHY parameters indicates using default configuration. For signal quality optimization, please refer to Section 6 HW CTS Setting Process.

    4.1.4 Command Line Usage Examples

    U-Boot provides the scsi command set to operate SATA devices (SATA devices are recognized as SCSI devices in U-Boot).

    4.1.4.1 Device Scan and Information Query
    # Reset and scan SCSI bus to detect new or changed devices
scsi reset
scsi scan

# Display all available SCSI device information
scsi info

# Select or display current SCSI device ([dev] is device number)
scsi device [dev]

# Display partition table of specified device (displays all devices if dev not specified)
scsi part [dev]
    4.1.4.2 Data Read/Write Operations
    # Read data from SCSI device to memory
# Usage: scsi read <memory address> <start block#> <block count>
scsi read addr blk# cnt

# Write data from memory to SCSI device
# Usage: scsi write <memory address> <start block#> <block count>
scsi write addr blk# cnt
    4.1.4.3 FAT File System Operations
    # List root directory files of SCSI device (device number 0)
fatls scsi 0

# Load file from FAT file system to memory
# Usage: fatload scsi <device number> <memory address> <filename> <bytes> <position>
fatload scsi 0 addr filename bytes pos

# Write file to FAT file system
# Usage: fatwrite scsi <device number> <memory address> <filename> <bytes> <offset>
fatwrite scsi 0 addr filename bytes offset
    4.1.4.4 Usage Examples
    # Complete U-Boot SATA boot flow example
=> scsi reset
=> scsi scan
=> scsi info
=> scsi part 0
=> fatls scsi 0:1
=> fatload scsi 0:1 0x23000000 kernel.bin
=> bootm 0x23000000

    ⚠️ Note:

    • SATA devices are accessed through the SCSI subsystem in U-Boot
    • Must execute scsi reset and scsi scan before use
    • Device numbering usually starts from 0

    5. Kernel Usage

    This section introduces the configuration and usage of the SATA Host driver during the Linux Kernel stage.

    5.1 Driver Configuration

    5.1.1 menuconfig Configuration

    Execute make menuconfig in the Linux Kernel source directory and enable the SATA driver following the path below:

    Device Drivers
├── SCSI device support --->
│   ├── [*] SCSI device support
│   ├── [*] legacy /proc/scsi/support
│   └── [*] SCSI disk support
│
├── [*] Serial ATA and Parallel ATA drivers (libata)
│   ├── [*] SATA Port Multiplier support
│   └── [*] Platform AHCI SATA support
│
└── [*] SGS SoC platform drivers --->
    ├── [*]   Sgs ACP Bridge driver
    └── [*]   Sgs SATA HOST
        ├── [*]     Sgs sata apply hd link
        └── [*]     Sgs sata apply hd link vote

    💡 Note:

    • After selecting the above options, the SATA driver will be compiled into the kernel (Built-in)
    • If compiled as modules (M), two module files drv-sata-host.ko and drv-sata-phy.ko will be generated

    5.1.2 DTS Node Configuration

    Add the following node configuration in the Kernel device tree file. Note: Compared to U-Boot DTS, Kernel DTS requires additional interrupt and clock configurations.

    5.1.2.1 SATA Port0 Configuration
    /* SATA Port0 PHY configuration */
sgs_sataphy: sgs-sata-phy {
    compatible = "sgs,sataphy";
    reg-names = "phyd", "phya", "phya2", "ahci_misc";  /* Note order differs from U-Boot */
    reg = <0x0 0x1F287600 0x200>, <0x0 0x1F287800 0x200>,
          <0x0 0x1F287a00 0x200>, <0x0 0x1F287400 0x200>;

    /* PHY parameter configuration */
    phy_mode = <2>;
    tx_ssc_mode = <0>;
    tx_gen1_gen2_Vpp = <0xFF>,<0xFF>;
    tx_gen3_de_emphasis = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_rs1 = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_rs2 = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_ctle = <0xFF>;

    port_id = <0>;
    #phy-cells = <0>;
    status = "ok";  /* Kernel uses "ok" instead of "okay" */
};

/* SATA Port0 AHCI controller configuration */
sata {
    compatible = "sgs,sata";
    reg-names = "ahci", "ahci_port0";
    reg = <0x0 0x1F346800 0x100>, <0x0 0x1F346900 0x100>;

    interrupts = <GIC_SPI INT_IRQ_SATA_MAC IRQ_TYPE_LEVEL_HIGH>;  /* Interrupt configuration */

    clocks = <&CLK_sata_pm>,      /* Power management clock */
             <&CLK_sata_phy_108>,  /* PHY 108M clock */
             <&CLK_sata_phy_200>,  /* PHY 200M clock */
             <&CLK_sata_phy_432>;  /* PHY 432M clock */

    phy-names = "sataphy";
    phys = <&sgs_sataphy>;

    fbs_mode;
    sata_acp;
    dma-coherent;
};
    5.1.2.2 SATA Port1 Configuration
    /* SATA Port1 PHY configuration */
sgs_sata1phy: sgs-sata1-phy {
    compatible = "sgs,sataphy";
    reg-names = "phyd", "phya", "phya2", "ahci_misc";
    reg = <0x0 0x1F288400 0x200>, <0x0 0x1F288600 0x200>,
          <0x0 0x1F288800 0x200>, <0x0 0x1F288200 0x200>;

    phy_mode = <2>;
    tx_ssc_mode = <0>;
    tx_gen1_gen2_Vpp = <0xFF>,<0xFF>;
    tx_gen3_de_emphasis = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_rs1 = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_rs2 = <0xFF>,<0xFF>,<0xFF>;
    rx_eq_ctle = <0xFF>;

    port_id = <1>;
    #phy-cells = <0>;
    status = "ok";
};

/* SATA Port1 AHCI controller configuration */
sata1 {
    compatible = "sgs,sata";
    reg-names = "ahci", "ahci_port0";
    reg = <0x0 0x1F346A00 0x100>, <0x0 0x1F346B00 0x100>;

    interrupts = <GIC_SPI INT_IRQ_SATA2_MAC IRQ_TYPE_LEVEL_HIGH>;

    clocks = <&CLK_sata2_pm>,
             <&CLK_sata2_phy_108>,
             <&CLK_sata2_phy_200>,
             <&CLK_sata2_phy_432>;

    phy-names = "sata1phy";
    phys = <&sgs_sata1phy>;

    fbs_mode;
    sata_acp;
    dma-coherent;
};

    5.1.3 DTS Parameter Description

    5.1.3.1 AHCI Controller Parameters (Kernel Additional Configuration)
    Property Description Needs Modification
    compatible Used for driver matching ❌ Do not modify
    #address-cells Child node address information length ❌ Do not modify
    #size-cells Child node address range length ❌ Do not modify
    interrupts Interrupt number and trigger type ❌ Do not modify
    clocks Clock source references ❌ Do not modify
    reg Register address and size ❌ No need to modify
    reg-names Register region name list ❌ No need to modify
    phys Referenced PHY node ❌ No need to modify
    phy-names PHY name list ❌ No need to modify
    fbs_mode Enable FIS-Based Switching mode ✅ Modify based on requirements
    sata_acp Enable ACP mode ❌ No need to modify
    dma-coherent Enable DMA coherency optimization ❌ No need to modify
    5.1.3.2 PHY Parameters (Kernel Additional Configuration)
    Property Description Configurable Values Needs Modification
    compatible Used for driver matching "sgs,sataphy" ❌ Do not modify
    reg Register address and size Fixed address ❌ No need to modify
    reg-names Register region name list "phyd","phya","phya2","ahci_misc" ❌ No need to modify
    phy_mode PHY rate mode 0=GEN1, 1=GEN2, 2=GEN3 ✅ Modify based on requirements
    tx_ssc_mode Spread spectrum clock mode 0=disabled, 1=enabled ✅ Modify based on requirements
    tx_gen1_gen2_Vpp GEN1/GEN2 transmit voltage swing 0xFF=default ✅ Adjust based on signal quality
    tx_gen3_de_emphasis GEN3 de-emphasis parameters See Section 6 CTS settings ✅ Adjust based on signal quality
    rx_eq_ctle Receive equalization parameter CTLE See Section 6 CTS settings ✅ Adjust based on signal quality
    rx_eq_rs1 Receive equalization parameter RS1 See Section 6 CTS settings ✅ Adjust based on signal quality
    rx_eq_rs2 Receive equalization parameter RS2 See Section 6 CTS settings ✅ Adjust based on signal quality
    status PHY enable status "ok" / "disabled" ✅ Optional modification

    5.1.4 Module Loading Order

    If the SATA driver is compiled as kernel modules (.ko files), load them in the following order:

    # 1. Load PHY driver first
insmod drv-sata-phy.ko

# 2. Then load AHCI Host driver
insmod drv-sata-host.ko

    ⚠️ Note:

    • Must load drv-sata-phy.ko first, then load drv-sata-host.ko
    • If the driver is compiled as Built-in, no manual module loading is required
    • After successful module loading, the system will automatically recognize connected SATA devices

    6. HW CTS Settings

    This section introduces how to perform SATA signal quality tuning through the Sysfs interface. CTS (Compliance Test Suite) settings are used to optimize PHY layer transmission parameters to ensure signal integrity.

    🎯 Objective: Optimize SATA signal quality by adjusting PHY parameters to resolve issues such as connection instability and transmission errors.

    6.1 Setting Process Overview

    HW CTS setting consists of the following steps that must be executed in order:

    1️⃣ Set transfer speed mode
   ↓
2️⃣ Set test pattern
   ↓
3️⃣ Set TX parameters (de-emphasis and voltage swing)
   ↓
4️⃣ Update optimized parameters to DTS

    ⚠️ Note: The transfer speed (test_gen) must be set before the test pattern (cts_pattern). The PHY driver requires the speed information before entering CTS pattern mode to correctly perform force speed.

    6.2 Sysfs Interface Paths

    CTS settings are completed through the Sysfs interface, with nodes located at:

    # SATA Port0
cd /sys/devices/virtual/sgs/sata0

# SATA Port1
cd /sys/devices/virtual/sgs/sata1

    6.3 Step 1: Set Transfer Speed Mode

    6.3.1 Speed Mode Description

    test_gen Value Transfer Rate Description
    0 1.5 Gbps SATA GEN1
    1 3.0 Gbps SATA GEN2
    2 6.0 Gbps SATA GEN3

    6.3.2 Configuration Method

    # 1. View current speed mode
cat test_gen

# 2. Set to GEN1 (1.5 Gbps)
echo 0 > test_gen

# 3. Set to GEN2 (3.0 Gbps)
echo 1 > test_gen

# 4. Set to GEN3 (6.0 Gbps)
echo 2 > test_gen

    6.4 Step 2: Set Test Pattern

    6.4.1 Pattern Type Description

    Pattern Value Pattern Name Description
    0 HFTP High Frequency Test Pattern
    1 MFTP Mid Frequency Test Pattern
    2 LFTP Low Frequency Test Pattern
    3 LBP Low Bit Pattern
    4 SSOP Spread Spectrum Oscillation Pattern

    6.4.2 Configuration Method

    # 1. View current Pattern setting
cat cts_pattern

# 2. Set Pattern (e.g., set to HFTP)
echo 0 > cts_pattern

# 3. Set Pattern (e.g., set to MFTP)
echo 1 > cts_pattern

    6.5 Step 3: Set TX Parameters

    TX parameters include de-emphasis and voltage swing (Vpp), used to optimize signal quality.

    6.5.1 Parameter Format

    echo [enable] [db] [level] > de_emphasis
    Parameter Description Optional Values
    enable GEN3 de-emphasis enable 0=Vpp only, 1=use de-emphasis
    db De-emphasis level (only valid when enable=1) 0~3
    level Voltage swing level 0~8

    6.5.2 De-emphasis Level Description

    db Value De-emphasis Strength Applicable Scenario
    0 -1.5 dB Short distance transmission
    1 -2.5 dB Medium distance transmission
    2 -3.5 dB Medium-long distance transmission
    3 -6.0 dB Long distance transmission

    6.5.3 Voltage Swing Description

    level Value Voltage Swing Supports GEN1 Supports GEN2 Supports GEN3
    0 0.4 Vpp ✅ ✅ ✅
    1 0.5 Vpp ✅ ✅ ✅
    2 0.6 Vpp ✅ ✅ ✅
    3 0.7 Vpp ✅ ✅ ✅
    4 0.8 Vpp ✅ ✅ ✅
    5 0.9 Vpp ❌ ✅ ✅
    6 1.0 Vpp ❌ ❌ ✅
    7 1.1 Vpp ❌ ❌ ✅
    8 1.2 Vpp ❌ ❌ ✅

    ⚠️ Note:

    • GEN1/GEN2 only support Vpp adjustment (level 0~4 or 0~5)
    • GEN3 supports both Vpp and de-emphasis adjustment
    • De-emphasis function is only available in GEN3 mode

    6.5.4 Configuration Examples

    Scenario 1: Vpp Adjustment Only (Common for GEN1/GEN2/GEN3)
    # GEN1/GEN2: Use 0.7Vpp (without de-emphasis)
echo 0 0 3 > de_emphasis

# GEN3: Use 0.7Vpp (without de-emphasis)
echo 0 0 3 > de_emphasis
    Scenario 2: GEN3 with De-emphasis
    # GEN3: -1.5dB de-emphasis + 0.7Vpp
echo 1 0 3 > de_emphasis

# GEN3: -3.5dB de-emphasis + 0.8Vpp
echo 1 2 4 > de_emphasis

# GEN3: -6.0dB de-emphasis + 1.0Vpp (long distance transmission)
echo 1 3 6 > de_emphasis

    6.6 DTS Parameter Mapping

    After completing CTS testing and confirming optimal parameters, you need to update the parameters to the device tree file.

    6.6.1 Parameter Correspondence

    Sysfs command format: echo [enable] [db] [level] > de_emphasis

    Corresponding DTS parameters:

    tx_gen3_de_emphasis = <[enable]>, <[db]>, <[level]>;

    6.6.2 Special Value Description

    Value Meaning Usage Scenario
    0xFF Use default value When not performing signal optimization
    0x00~0x03 db level Valid when enable=1
    0x00~0x08 level level Voltage swing level

    6.6.3 DTS Configuration Examples

    Example 1: Using Default Configuration
    tx_gen3_de_emphasis = <0xFF>, <0xFF>, <0xFF>;
    Example 2: GEN3 with Vpp Only (No De-emphasis)
    /* enable=0 (Vpp only), db ignored, level=3 (0.7Vpp) */
tx_gen3_de_emphasis = <0>, <0xFF>, <3>;
    Example 3: GEN3 with De-emphasis
    /* enable=1 (enable de-emphasis), db=1 (-2.5dB), level=4 (0.8Vpp) */
tx_gen3_de_emphasis = <1>, <1>, <4>;

/* enable=1 (enable de-emphasis), db=3 (-6.0dB), level=6 (1.0Vpp) */
tx_gen3_de_emphasis = <1>, <3>, <6>;
    Example 4: GEN1/GEN2 Configuration
    /* GEN1/GEN2 use Vpp only, no de-emphasis */
tx_gen1_gen2_Vpp = <3>, <3>;  /* Two values correspond to GEN1 and GEN2 respectively */

/* GEN3 de-emphasis parameters remain default (when only GEN1/GEN2 are effective) */
tx_gen3_de_emphasis = <0xFF>, <0xFF>, <0xFF>;

    6.7 Complete Configuration Process Example

    Assume the optimal parameters determined through testing are: GEN3 mode, -2.5dB de-emphasis, 0.8Vpp

    Step 1: Verify Parameters via Sysfs

    # 1. Enter SATA sysfs directory
cd /sys/devices/virtual/sgs/sata0

# 2. Set speed to GEN3
echo 2 > test_gen

# 3. Set test pattern to MFTP
echo 1 > cts_pattern

# 4. Set TX parameters: -2.5dB de-emphasis + 0.8Vpp
echo 1 1 4 > de_emphasis

# 5. Perform signal quality testing (using oscilloscope or other test equipment)
# If testing passes, the parameter configuration is correct

    Step 2: Update to Device Tree

    Write the verified parameters to the device tree file:

    sgs_sataphy: sgs-sata-phy {
    compatible = "sgs,sataphy";
    reg-names = "phyd", "phya", "ahci_misc", "phya2";
    reg = <0x1F287600 0x200>, <0x1F287800 0x200>,
          <0x1F287400 0x200>, <0x1F287a00 0x200>;

    phy_mode = <2>;                      /* GEN3 mode */
    tx_ssc_mode = <0>;

    /* GEN1/GEN2 Vpp configuration */
    tx_gen1_gen2_Vpp = <0xFF>, <0xFF>;   /* Use default values */

    /* GEN3 configuration: -2.5dB de-emphasis + 0.8Vpp */
    tx_gen3_de_emphasis = <1>, <1>, <4>;

    /* RX equalization parameters (can also be adjusted if needed) */
    rx_eq_rs1 = <0xFF>, <0xFF>, <0xFF>;
    rx_eq_rs2 = <0xFF>, <0xFF>, <0xFF>;
    rx_eq_ctle = <0xFF>;

    port_id = <0>;
    #phy-cells = <0>;
    status = "okay";
};

    Step 3: Recompile and Test

    # 1. Recompile
# 2. Update device tree to target board
# 3. Restart system
# 4. Verify SATA device works properly

    6.8 FAQ

    Q1: How to determine if CTS parameters need adjustment?

    Symptoms:

    • SATA device not recognized
    • Timeouts or CRC errors during transmission
    • High-speed transmission (GEN3) unstable

    Solutions:

    1. Try reducing speed first (GEN3 → GEN2 → GEN1)
    2. Adjust Vpp value (increase voltage swing)
    3. Enable de-emphasis function (GEN3)

    Q2: When should the enable parameter be set to 0 or 1?

    • enable=0: Use Vpp adjustment only, applicable to GEN1/GEN2 or scenarios without de-emphasis
    • enable=1: Enable de-emphasis, only applicable to GEN3 long-distance transmission or poor signal quality scenarios

    Q3: How to choose the appropriate level value?

    level Voltage Recommended Scenario
    0~2 0.4~0.6V Short distance transmission (<0.5m)
    3~4 0.7~0.8V Medium distance (0.5~1m)
    5~8 0.9~1.2V Long distance (>1m) or poor signal

    Q4: Do RX equalization parameters need adjustment?

    Normally, TX parameters (Vpp and de-emphasis) are sufficient. Only consider adjusting RX equalization parameters (rx_eq_rs1, rx_eq_rs2, rx_eq_ctle) when issues persist after TX parameter adjustment.