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Power Consumption Adjustment Guide

REVISION HISTORY

Revision No.
Description
 Date
1.0
  • Initial release
    		•  04/08/2025
    1.1
  • Add idac voltage adjustment section
    		•  08/18/2026

    1. Overview

    This document is provided as a guide to the power consumption optimization of the SGS PureLinux platform. An introduction of the clock switch and frequency adjustment method is provided for each module.

    2. Configuration

    The PureLinux platform is currently connected to the CCF(Common Clock Framework), and by default unused modules will be disabled during the Linux system startup phase.

    But you need to make sure to enable the following configuration:

    PureLinux:

    Symbol: COMMON_CLK [=y]
Type  : bool
Defined at drivers/clk/Kconfig:21
  Prompt: Common Clock Framework
  Depends on: !HAVE_LEGACY_CLK [=n]

    After the above configuration is enabled, clock enable/disable and clock dependencies will be taken over by CCF. Each module only needs to be connected with the interface provided by CCF. For users, the points that need attention are mainly divided into:

    1. Module Addition and Removal

      Most BSP modules will enable the clock when they are in use, but some modules will enable the clock during the loading phase (probe). These modules need to ensure that they are not loaded when not in use, such as the USB module.

    2. Module Frequency Adjustment

      This part is mainly aimed at streaming modules with high power consumption. Users can adjust the appropriate frequency suitable for the scene to reduce power consumption.

    In addition, some special modules will be introduced in further detail, such as CPU and IDAC.

    2.1. Module Addition and Removal

    This section introduces the configuration and operation for adding and removing modules.

    2.1.1. usb

    USB will be divided into host-side controller and device-side controller, which will be introduced separately here.

    usb 2.0 host controller:

    Symbol: USB_EHCI_HCD [=m]
Type  : tristate
Defined at drivers/usb/host/Kconfig:129
  Prompt: EHCI HCD (USB 2.0) support
  Depends on: USB_SUPPORT [=y] && USB [=y] && HAS_DMA [=y] && HAS_IOMEM [=y]
  Location:
    -> Device Drivers
      -> USB support (USB_SUPPORT [=y])
  Corresponding module driver: ehci-hcd.ko

    usb 2.0 device side controller:

    Symbol: USB_SGS_MSB250X_UDC [=m]
Type  : tristate
Defined at drivers/sgs_common/usb/gadget/udc/usb20/Kconfig:1
  Prompt: Sgs MSB250X USB 2.0 Device Controller
  Depends on: USB_SUPPORT [=y] && USB_GADGET [=m]
  Location:
    -> Device Drivers
      -> USB support (USB_SUPPORT [=y])
        -> USB Gadget Support (USB_GADGET [=m])
          -> USB Peripheral Controller
  Corresponding module driver: udc-msb250x.ko

    usb 3.0 host controller:

    Symbol: USB_XHCI_HCD [=m]
Type  : tristate
Defined at drivers/usb/host/Kconfig:20
  Prompt: xHCI HCD (USB 3.0) support
  Depends on: USB_SUPPORT [=y] && USB [=y] && HAS_DMA [=y] && HAS_IOMEM [=y]
  Location:
    -> Device Drivers
      -> USB support (USB_SUPPORT [=y])
  Corresponding module driver:xhci-hcd.ko xhci-plat-hcd.ko

    usb 3.0 device side controller:

    Symbol: USB_DWC3 [=m]
Type  : tristate
Defined at drivers/usb/dwc3/Kconfig:3
  Prompt: DesignWare USB3 DRD Core Support
  Depends on: USB_SUPPORT [=y] && (USB [=y] || USB_GADGET [=n]) && HAS_DMA [=y] && (EXTCON [=y] || EXTCON [=y]=n [=n])
  Location:
    -> Device Drivers
     -> USB support (USB_SUPPORT [=y])
  Corresponding module driver:dwc3.ko

    2.1.2. sdmmc

    Symbol: SGS_SDMMC [=m]                                                                                                        Type  : tristate
Defined at drivers/sgs_common/sdmmc/Kconfig:1
  Prompt: Sgs SD/MMC Card Interface Support
  Depends on: SGS_DRIVERS [=y] && MMC [=m]
  Location:
    -> Device Drivers
      -> Sgs SoC platform drivers (SGS_DRIVERS [=y])
  Corresponding module driver: kdrv_sdmmc.ko

    2.1.3. gmac

    Symbol: SGS_GMAC [=y]
Type  : tristate
Defined at drivers/sgs_common/gmac/Kconfig:2
  Prompt: SGS GMAC
  Depends on: SGS_DRIVERS [=y] && SGS_OS_NAME [=lnx]=lnx
  Location:
    -> Device Drivers
      -> Sgs SoC platform drivers (SGS_DRIVERS [=y])
        -> SGS GMAC
  Corresponding module driver: sgs_gmac.ko

    2.2. Module Frequency Adjustment

    All modules listed in this chapter support frequency adjustment. Modules related to streaming are mainly divided into Debug interface and Formal interface.

    Debug interface supports Clock Level Viewing and Clock Level Configuration.

    • This interface is only used to adjust the appropriate clock frequency. The displayed clock is divided into two parts, the clock source level and the current clock frequency. Since the module clock may support divider, the actual clock may be the clock source subdivision level.
    • This type of interface needs to ensure that the mi_debug function is enabled. For example, if you need to enable the VENC function, you need to make sure that CONFIG_ENABLE_VENC_DEBUG is enabled.

    Formal interface is set through modparam.json:

    • After confirming the clock through the debugging interface, configure it through this interface. This interface supports purelinux settings. modparam.json is a unified initialization interface. For detailed usage, please see the mi_common usage.

    Tips for confirming clock level

    • Clock level: The module clock level viewing only provides the level of the clock source. Some modules support divider, so there will be more clock levels (based on clock source frequency division). During actual configuration, you can first confirm whether the large clock source level meets the requirements, and then subdivide and configure smaller clock levels.

    • The clock frequency required for module processing tasks is related to the frame rate and image resolution of the hardware processing, so there is no way to give a relatively unified formula level to estimate the clock frequency. Therefore, the current way to obtain the clock frequency is to constantly try to configure the level, confirm whether the module is working properly, and gradually approach the final level. It can be roughly divided into the following steps:

      1. In the complete scene, based on the normal working condition of the scene, obtain the basic clock frequency at this time

      2. Start adjusting the clock frequency from the front-end module. It needs to be based on the basic clock frequency and proceed from high to low until a suitable clock is obtained.

        If the frame rate of the module decreases, or problems such as fifo full occur, it means that the clock frequency has reached the bottom. At this time, the relevant clock level needs to be adjusted to a higher level; if the scene is a hardware direct connection mode, the direct connection mode can be switched to frame mode to avoid mutual influence between front and rear stages

      3. Increase the obtained clock frequency by a margin

        Because the clock frequency is continuously debugged, it will tend to be the limit frequency value of the hardware processing in this scene. If the bandwidth is reduced or the scene is fine-tuned, the frame rate of the module processing may be insufficient, so it is necessary to add appropriate margin to the frequency adjusted in the second step at this time .

    2.2.1. vdec

    Clock Level Viewing:

    / # cat /proc/mi_modules/mi_vdec/debug_hal/vdec_clock
-------VDEC Device [0]---------
 600000000 vpll od
 540000000 vpll od
 504000000 vpll <--
 432000000 vpll
 348000000 vpll
 300000000 vpll
 576000000 od
 480000000
 384000000

-------VDEC Device [1]---------
 600000000 vpll od
 540000000 vpll od
 504000000 vpll <--
 432000000 vpll
 348000000 vpll
 300000000 vpll
 576000000 od
 480000000
 384000000

    Clock Level Configuration:

    Dev0 and dev1 share the same PLL clock, so all devices using this clock will be modified synchronously during adjustment.

    / # echo 432000000 > /proc/mi_modules/mi_vdec/debug_hal/vdec_clock
/ # cat /proc/mi_modules/mi_vdec/debug_hal/vdec_clock
-------VDEC Device [0]---------
 600000000 vpll od
 540000000 vpll od
 504000000 vpll
 432000000 vpll <--
 348000000 vpll
 300000000 vpll
 576000000 od
 480000000
 384000000

-------VDEC Device [1]---------
 600000000 vpll od
 540000000 vpll od
 504000000 vpll
 432000000 vpll <--
 348000000 vpll
 300000000 vpll
 576000000 od
 480000000
 384000000

    Formal interface:

    {
    "E_MI_MODULE_ID_VDEC" :
    {
        "vdec_clock": 432000000
    }
}

    2.2.2.scl

    Clock Level Viewing:

    / # cat /proc/mi_modules/mi_scl/debug_hal/clk 
[0] 240000000
[1] 288000000
[2] 320000000
[3] 345000000
[4] 384000000
[5] 432000000
[6] 480000000
[7] 576000000 <-------

    Clock Level Configuration:

    / # echo 384000000 > /proc/mi_modules/mi_scl/debug_hal/clk
/ # cat /proc/mi_modules/mi_scl/debug_hal/clk
[0] 240000000
[1] 288000000
[2] 320000000
[3] 345000000
[4] 384000000 <-------
[5] 432000000
[6] 480000000
[7] 576000000

    Formal interface:

    {
    "E_MI_MODULE_ID_SCL" :
    {
        "scl_clk": 384000000
    }
}

    2.2.3.venc

    Clock Level Viewing:

    / # cat /proc/mi_modules/mi_venc/debug_hal/ven_clock
 480000000 <--
 432000000
 384000000
 288000000
Current CLK: 480000000  (dfs=0/0, source=480000000)

    Clock Level Configuration:

    / # echo 432000000 > /proc/mi_modules/mi_venc/debug_hal/ven_clock 
/ # cat /proc/mi_modules/mi_venc/debug_hal/ven_clock 
 480000000
 432000000 <--
 384000000
 288000000
Current CLK: 432000000  (dfs=0/0, source=432000000)

    Formal interface:

    {
    "E_MI_MODULE_ID_VENC" :
    {
        "ven_clock": 432000000,
    }
}

    2.2.4.jpe

    Clock Level Viewing:

    // # cat /proc/mi_modules/mi_venc/debug_hal/jpe_clock
-------Device 0---------
 384000000 <--
 345000000
 320000000
 288000000
 216000000
 172000000
Current CLK: 384000000  (dfs=0/0, source=384000000)

    Clock Level Configuration:

    / # echo 345000000 > /proc/mi_modules/mi_venc/debug_hal/jpe_clock 
/ # cat /proc/mi_modules/mi_venc/debug_hal/jpe_clock 
-------Device 0---------
 384000000
 345000000 <--
 320000000
 288000000
 216000000
 172000000
Current CLK: 345000000  (dfs=0/0, source=345000000)

    Formal interface:

    {
    "E_MI_MODULE_ID_VENC" :
    {
        "jpe_clock": 345000000
    }
}

    2.2.5. ipu

    Clock Level Viewing:

    / # cat /proc/mi_modules/mi_ipu/debug_hal/freq 
current ipu clock frequency: 800MHz
available frequency:
800MHz
700MHz
680MHz
600MHz
500MHz
400MHz
300MHz

    Clock Level Configuration:

    / # echo 500 > /proc/mi_modules/mi_ipu/debug_hal/freq
/ # cat /proc/mi_modules/mi_ipu/debug_hal/freq
current ipu clock gear: 500MHz
available frequency:
800MHz
700MHz
680MHz
600MHz
500MHz
400MHz
300MHz

    Formal interface:

    {
    "E_MI_MODULE_ID_IPU" :
    {
        "ipu_clk": 500000000
    }
}

    2.2.6.ive

    Clock Level Viewing:

    / # cat /proc/mi_modules/mi_ive/debug_hal/ive_clk 

---------- IVE clock -----------
432000000 <--
288000000
480000000
Current CLK: 432000000 dfs(0/0, src=432000000)

    Clock Level Configuration:

    / # echo 288000000 > /proc/mi_modules/mi_ive/debug_hal/ive_clk
/ # cat /proc/mi_modules/mi_ive/debug_hal/ive_clk
---------- IVE clock -----------
432000000
288000000 <--
480000000
Current CLK: 288000000 dfs(0/0, src=288000000)

    Formal interface:

    {
    "E_MI_MODULE_ID_IVE" :
    {
        "ive_clk": 288000000
    }
}

    2.3. cpu

    CPU frequency adjustment is currently performed through the Linux cpufreq subsystem, so this section mainly introduces the interface provided by cpufreq.

    Need to ensure that the configuration CONFIG_MS_CPU_FREQ is enabled.

    2.3.1. Node Introduction

    Node path: /sys/devices/system/cpu/cpufreq/policy0

    Node name Function
    cpuinfo_cur_freq The current operating frequency of the CPU, generally equal to scaling_cur_freq
    cpuinfo_max_freq The highest operating frequency supported by the CPU
    cpuinfo_min_freq The lowest operating frequency supported by the CPU
    scaling_available_frequencies Frequency levels supported by the regulator:
    600000 700000 800000 900000 1000000 1100000 1200000 1300000 1400000 1500000 1600000
    scaling_cur_freq The current CPU operating frequency determined by the regulator
    scaling_available_governors Supported adjustment strategies:
    1. performance: performance-first mode, does not consider power consumption, only uses the highest frequency
    2. powersave: power-saving mode, usually runs at the lowest frequency
    3. userspace: user-defined mode, supports manual frequency adjustment in user space
    4. ondemand: on-demand mode, periodically checks the load and adjusts frequency according to the load
    scaling_governor View the current adjustment strategy and set the adjustment strategy, the default is userspace
    scaling_max_freq The highest CPU operating frequency supported by the regulator
    scaling_min_freq The lowest CPU operating frequency supported by the regulator
    scaling_setspeed If the selected adjustment strategy is userspace, you can set the CPU operating frequency to a certain value

    2.3.2. Configuration Constraints

    1. scaling_min_freq must be less than or equal to scaling_max_freq
    2. scaling_min_freq must be greater than or equal to cpuinfo_min_freq
    3. scaling_max_freq must be less than or equal to cpuinfo_max_freq
    4. scaling_setspeed must be within the range of scaling_min_freq and scaling_max_freq

    2.3.3. Setting Frequency

    # Configure the current governor as userspace
/sys/devices/system/cpu/cpufreq/policy0/ # echo userspace > scaling_governor

# Confirm whether the frequency to be configured is within the range:
/sys/devices/system/cpu/cpufreq/policy0 # cat scaling_min_freq
600000
/sys/devices/system/cpu/cpufreq/policy0 # cat scaling_max_freq
1600000

# Configure the current frequency
/sys/devices/system/cpu/cpufreq/policy0 # echo  1000000 > scaling_setspeed
/sys/devices/system/cpu/cpufreq/policy0 # cat scaling_cur_freq
1000000

    2.4. idac

    The SGS platform supports fine-grained voltage adjustment of the power rails such as Core Power (VDD_CORE), CPU Power (VDD_CPU) and IPU Power (VDD_IPU) through IDAC, with an adjustment accuracy of 10mV or 20mV. Lowering the operating voltage appropriately while meeting the working requirements of each module can further reduce the overall power consumption. The adjustable power rails supported by different platforms may vary. For the hardware connection, driver configuration and voltage adjustment methods of IDAC, please refer to IDAC USER GUIDE.